1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems including trace mechanisms operable to generate a trace data indicative of the behaviour and state of the data processing system being monitored.
2. Description of the Prior Art
It is known to provide data processing systems with trace mechanisms, such as the ETM systems designed by ARM Limited of Cambridge, England, that operate in conjunction with integrated circuit designs and SoC designs. As system designs become more complex, it is possible to have multiple sources of trace data within a system each generating their own stream of trace data. This trace data is typically then collected and routed out of the integrated circuit in a concatenated stream of trace data. In view of pin count constraints, it is not practical to provide separate dedicated outputs for each trace data source.
Within such a system having multiple trace data sources, it is desirable that they should include an ability to buffer their own trace data stream until an opportunity becomes available for this trace data stream to be output from the integrated circuit. Some trace data sources may have higher priority than other trace data sources and accordingly low priority trace data sources may need to buffer their trace data output for a significant amount of time.
Whilst the above approach is able to provide trace data monitoring of multiple elements within an overall system and work with a limited output capability from the integrated circuit, problems arise in that in some circumstances the trace data as it emerges from the integrated circuit may not include all of the data of interest around a particular operational point being investigated. Furthermore, changes of state or mode between different areas of the system may be inhibited due to the pending storage of trace data within areas of the integrated circuit which are to have their operational state or mode altered.